[Rtai] SMI-Module Control Question

[Mayer, Eric (US SSA)]

Hello RTAI Team,

   I have been bringing up a legacy system and have been having problems (RH9 w/Kernel 2.4.20 and RTAI 24.1.11 RTHAL).  The controller we have happens to be working with an ICH4 chipset.  I was looking at the SMI work around (smi-module) and the README.SMI comment from Jason related to his short cut as follows:


README.SMI -> Instructions:



        1. The GBL_SMI_EN bit in the SMI_EN register must be cleared.

        2. The TCO_TMR_HLT bit in the TCO1_CNT register must be set.
---
http://www.rtai.dk/cgi-bin/gratiswiki.pl?Hardware
EMAIL -> According to the ICH4 (that's the main controller chip) spec, it is possible
to disable SMI interrupts.  The ICH4 has all its registers mapped to I/O
space so it's just a matter of calling "outb" from your module.  In my
system, I have used the following calls to disable SMI:

outb(0x08, 0x469);  /* Disable watchdog timer in the ICH4 */
outb(0x3a, 0x430);  /* Clear the GBL_SMI_ENA bit */

... So my question is how does the Smi-module modify the watch dog timer (TCO_TMR_HLT?) setting in the 0x08 (TCO_CNT?) register?  Or should the user set the masks in Smi-module and then perform a dedicated write to the Watch Dog.

Thanks,
Eric Mayer

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